Pipelined analog-to-digital converters (ADC's) have become popular ADC architectures for sampling rates from a few mega-samples per second (MSPS) to over one hundred MSPS. Resolutions typically range from eight bits at the faster sample rates up to 16 bits at the lower rates. A pipelined ADC uses two or more steps of subranging, where each stage is responsible for quantizing a number of bits and generating an amplified residue. For example, sample-and-hold samples and holds steady an analog input (VIN), while an ADC in a first stage coarsely quantizes it to a predetermined number of bits. When a given stage finishes processing a sample, determining the bits, and passing the residue to the next stage, it can then start processing the next sample received from the sample-and-hold embedded within each stage. This pipelining action is one reason for the high throughput of the ADC.
In high speed, switched capacitor based ADCs with a current DAC reference in each stage of the pipeline, for example, DAC settling (e.g., time for DAC output to stabilize after DAC input code changed) is expected to be much faster than residue amplifier settling in order to generate an accurate residue in the given hold time for the ADC. However, due to large capacitive loads that DAC reference has to drive, it becomes necessary to consume a lot of power to provide faster DAC settling and overcome the capacitive load. This results in increasing the sizes of DAC switches, DAC current sources, and the power used in the DAC driver circuit.